Electronic Lab

perl-Verilog-Readmem - Parse Verilog $readmemh or $readmemb text file

Website: http://search.cpan.org/dist/Verilog-Readmem/
License: GPL+ or Artistic
Description:
The Verilog Hardware Description Language (HDL) provides a convenient way
to load a memory during logic simulation. The $readmemh() and $readmemb()
system tasks are used in the HDL source code to import the contents of a
text file into a memory variable.

Packages

perl-Verilog-Readmem-0.04-8m.mo7.noarch [13 KiB] Changelog by Yohsuke Ooi (2010-08-31):
- (0.04-8m)
- full rebuild for mo7 release

Listing created by Repoview-0.6.5-1m.mo7